Power Reduction in Pipeline Designs
نویسندگان
چکیده
The realization of fast datapaths in signal processing environments requires fastest logic styles with synchronous behavior. This paper presents a systematic method which efficiently combines improvements on algorithm and logic level. Thus, the design of power efficient, fast and synchronous pipelines is possible. To reduce the power consumption of dynamic logic, we show methods for single-rail structures utilizing redundant number systems. Therefore, we discuss the realization of self-timed structures with single-rail logic and redundant number systems and we present a new scheme which eases the understanding and construction of such self-timed structures. First simulations for a horizontal redundant adder slice show area and power savings of 40% and 30% compared to complementary Domino logic.
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